Honored ContributorHi all,
I did a lot of redesign to reduce the register count and ALUT count. But it still doesn't fit because of lack of LAB. Could anyone tell me something about LAB? What is that used for? Also, could someone look at my report and give me some hints on what I should to to make it fit? Thanks a lot!
Honored ContributorA LAB (Logic Array Block) is a block of (10, I thin) ALUTs.
The ALUTs in a LAB have some shared resources (global signals, interconnect) which add some restrictions. Thus, it is possible that even if you have enough ALUTs, your design can't be fitted because the ALUTs can't be properly grouped into LABs.Honored ContributorYou're still significantly over. Logicu Utilization is the key metric as it tries to incorporate all the dynamic issues of fitting logic, and it's at 118%. (Which is the same as the LAB overuse, but gives more info). You really need to remove logic. Your register count is almost at 100%, but not every register will be usable due to lab-wide control signals,# -lab inputs, etc. It is interesting that your register count is higher than your LUT count. Usually it's the opposite. If your design is really, really heavily pipelined, then its possible. Maybe look through the hierarchy brower and look for register counts and ALUT counts and see if there are any really large outliers, which might be a RAM that didn't get inferred. Probably not there, but worth a check. But most likely you have to remove logic or go to a larger part, I'm sorry to say.
Honored ContributorYeah. I know I've used a lot of registers and some of my design does use heavy pipelines. But I've noticed a weird thing in my report.
It's that the LUT REGs are less than 1 percent and the dedicated registers are nearly run out of. I suppose the LUT REGs are the Registers inside the ALM and paired with ALUTs. Why the tool didn't fully utilize those resources but resort to dedicated logic registers?Honored ContributorHere is the specific part of the report I was talking about.
; ALUTs Used ; 34,048 / 38,000 ( 90 % ) ; ; -- Combinational ALUTs ; 33,354 / 38,000 ( 88 % ) ; ; -- Memory ALUTs ; 554 / 19,000 ( 3 % ) ; ; -- LUT_REGs ; 140 / 38,000 ( < 1 % ) ; ; Dedicated logic registers ; 37,216 / 38,000 ( 98 % )Honored ContributorI never seen a report like that.
registers are either those of LUT pairs(dedicated) or io registers. It could be the report is saying you have used 37,216 dedicated but only 140 are used without pairingHonored ContributorHaving made some search it turns out that LUT_reg means something quite new to me. Some devices have LUT_reg mode where an LUT is converted to a register...i.e. register created from logic of LUT without using dedicated registers. This possibly indicate a famine of registers. So you may try lower the register count by redesign
Honored ContributorWithout actually seeing the design, its difficult to say much more than "Search through the design and trim bits out, or get a bigger chip".
Are you sure all rams have actually been placed in rams? could you not use a FIFO inside of some of your pipelining?Honored ContributorI did use some FIFO. But the FIFO should be memory not registers. And all the other Rams are synthesized correctly.
Thankfully we've decided we could move the design to a larger device.Honored ContributorLUT_RAM is a special capability of the LUT inside of an ALM having a feedback path that allows it to act like a FF instead of logic. It's not very useful, and not a good trade-off, but some designs that are extremely pipelined get some savings with it. They got rid of it for Stratix V and doubled the number of registers in the ALM.
