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Altera_Forum
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8 years ago

Design Compilation Report: Performance Results

I am using Intel FPGA SDK for OpenCL to compile my OpenCL design as follows: aoc -v --board a10gx my_kernel.cl -o my_kernel.aocx --report In the report I found board utilization estima...
Altera_Forum's avatar
Altera_Forum
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8 years ago

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What about simple Quartus II projects? I figured out how to use TimeQuest Timing Analyzer to calculate maximum frequency but I couldn't find anything on how to get latency metrics.

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If you are talking about HDL projects, you can calculate the latency manually by counting the number of register in your pipeline, and dividing that by post-place-and-route operating frequency.