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Altera_Forum's avatar
Altera_Forum
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12 years ago

Design Assistant

Hi, i have a question to the Quartus II Design Assistant.

In my design there is a reset synchronisation like this:

https://www.alteraforum.com/forum/attachment.php?attachmentid=7363

"async_res_in_n" is the asynchrounous external reset pin of my board and "sync_res_out_n" feeds all other registers in my designs.

This is what the Design Assistant wants to see.

But i always got the Warning Message:

Rule R102: External reset signals should be synchronized using two cascaded registers. Found 1 node(s) related to this rule.

Any idea ?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Have the same warning in my current design. On a reset signal that is syncronized with two cascaded registers.

    You probably can ignore it (Disable rule/Suppress).