Design assistant - reporting violating paths

Pletz,

I have a design with two very disparate clocks (125MHz and 7.8MHz). The 7.8MHz is generated in RTL, using a counter, which is based on the 125MHz clock. We chose to implement two "send and capture" signals based on this same counter to provide known points in time to "send" new data to the 7.8MHz domain and to "capture" data back from it, relative to the 125 domain. My concern is if we false-path the actual "data" flops, there will be no constraint on their transfer to the 7.8MHz domain. As such ,we implemented multicycle constraints, yet are still seeing the D101 critical warnings and are concerned the tool is not doing what we want it to and even perhaps over compensating.

Any ideas on how to approach this?