--- Quote Start ---
The design assistant has a few violating rules for clock crossings in our design. It lists the start point and endpoint, but doesn't list the path between the two.
I haven't seen any options yet to enable logging of the violating path, so you can see when the domain crossing happens. Does anyone know if it's possible to do so?
Thanks,
baver
--- Quote End ---
Hi Baver,
Critical Warning: (High) Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains. Found 8 asynchronous clock domain interface structure(s) related to this rule.
Critical Warning: Node "inst[7]"
Critical Warning: Node "inst[6]"
Critical Warning: Node "inst[5]"
Critical Warning: Node "inst[4]"
Critical Warning: Node "inst[3]"
Critical Warning: Node "inst[2]"
Critical Warning: Node "inst[1]"
Critical Warning: Node "inst[0]"
select one of the critical warning, right mouse clock -> locate e.g RTL view
Kind regards
GPK
Honored Contributor
