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Using not gates and logic to delay signals is a very bad idea. The actual delay is dependant upon the routing generated during compilation and temperature, so your delay will change every time you re-compile the chip.
It is much safer to use synchronous logic with extra timing specs attached to output pins if you really need to delay an output signal.
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I highly agree with you, and do not want to use it in production code. My only purpose was to discover whether similar (non-intentional)
situation could be (and should be?) discovered using waveform analyzis.
The other question about the timing arithmetics is just the consequence of the analyzis.
My quess was, that after compilation, the routing and delays are fixed, and can be calculated.
(and I am not interested whether in another compilation will be the same value)
Honored Contributor
