Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Delays and glitches in simulation

Hi, I wonder if I misunderstand something or the Qartus simulation is not able to consider state changes I want to display. I started with the Quartus demo program 'light'. I noticed that the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Using not gates and logic to delay signals is a very bad idea. The actual delay is dependant upon the routing generated during compilation and temperature, so your delay will change every time you re-compile the chip.

It is much safer to use synchronous logic with extra timing specs attached to output pins if you really need to delay an output signal.