Delaying all incoming signals by 2 ms using VHDL

That's not the only tricky part. The other tricky part going along with that one is the clock stability. Will the clock, 1,000,000 clocks later, be the 2ms you want at all times? Perhaps 2ms might wander between a delay of 0,999,900 and 1,000,100. If you want to keep the actual delay exact, then you'll need to be careful about what external source provides you with your clock.