Delaying all incoming signals by 2 ms using VHDL

Yes those constructs are used only for simulation, but they do not work as buffers either. They are meant to model the delay through a wire, so any other assignment in the mean time will override any previous assignment.

For your test you probably want to detect the edge of the pulses and then start off a counter to time the delay between the pulses. You can only be as accurate as the clock you are using for any logic, so for your case you can only be accurate to the nearest 20 ns.

2. Quartus has many IP blocks avaialble for free. See https://www.altera.com/support/literature/lit-ip.html for a looong list of altera IP. But from what you describe, you probably dont need a buffer, more like a detector and a counter.