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sslo0's avatar
sslo0
Icon for New Contributor rankNew Contributor
7 years ago

Delay in vhdl

hi, I am trying to delay an input signal by a certain time delay as follow but the problem when i simulate the signal is always delayed by 7.946 ns even if I change the time delay in the code...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

It should work fine, I have Checked it with modelsim. Also note that delay are not synthesizable.

Regards

Anand