Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Delay caused in RAM due to Latches

Dear friends,

The LPM RAM or RAM created using MEGAWIZARD has one latch for all the i/p's and also for the ouputs, due to which it causes two cycles dealy in reading the outputs. How to create the RAM without a latch or how to overcome this dealy due to latches in the input and output side, The FPGA we are using is CYCLONE 3.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    --- Quote Start ---

    Dear friends,

    The LPM RAM or RAM created using MEGAWIZARD has one latch for all the i/p's and also for the ouputs, due to which it causes two cycles dealy in reading the outputs. How to create the RAM without a latch or how to overcome this dealy due to latches in the input and output side, The FPGA we are using is CYCLONE 3.

    --- Quote End ---

    Hi,

    as far as I know at least the inputs must be registered . Cyclone III does not support asynchronoous Ram.

    Kind regards

    GPK