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The
advanced synthesis cookbook dicusses techniques to generate logic cell delays.
http://www.altera.com/literature/manual/stx_cookbook.pdf --- Quote End ---
I will take a look at that, thanks FvM.
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Hi,
why do you want to do that ? Do you want to know how large your positive slack on the path is ?
Kind regards
GPK
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Hi GPK, Yes that is exactly what I want to do. I know a path in the circuit that is between the two modules that is not the critical path, and I want to find out what the slack is between that path and the critical path. Is this functionality already available and I dont know about it?
-JV
Honored Contributor
