Deglitch Logic Metastability

Hi,

if a, b and c are asynchronous to i_clk, and you really want to prevent metastability, I'd say none of the three variants are safe.

Both in the first and the third code snippet, the filt_* signals are assigned directly from the asynchronous input signals a/b/c. If a/b/c happen to arrive too close to a clock edge of i_clk, the registers that hold the corresponding filt_* signal will go metastable, making subsequent logic fed by filt_* error-prone.

In the second case you have better metastability protection, but quite not 100%. Try to synthesize this code and open it in the RTL viewer. You'll see that the asynchronous a/b/c signals are registered (the abc_last register). Then there is a mux (which decides whether to feed abc_last into filt_* or not), and then the registers that hold filt_*.

The rule to prevent metastability is to have two registers in a rwo, with no logic in between. The first register can go metastable, indeed, but the metastable state will (with a huge probability) have settled once the signal is latched in the second register. If you have any logic in between, this logic will delay the metastable signal, making the probability higher that the signal arrives in an intermediate (metastable) state at the second register.

What I would recommend: use two registers to properly synchronize the a/b/c signals, and then chose any of your thee examples to do the deglitching.

Regarding your question whether or not this is over-thinking: for a small just-for-fun FPGA project I would not expect any problems ever with the second example. For a real-world FPGA project I'd say better safe than sorry. If you're designing an ASIC then you probably would even use three synchronization registers instead of only two.

Best regards,

GooGooCluster