Altera_ForumHonored Contributor11 years agoDefining Symbol-File in VHDL. Is this possible? Hi, I'm just curious, is there a way to describe how Quartus should create a Symbol-File in VHDL? :confused: My intention is to tell the "Symbol-File-Generator" that for example an Input h...Show More
Recent DiscussionsIs Quartus Prime Pro 22.4 Compatible with Stratix 10 NX Series Device?Timing analysis - long combinational pathQuartusPro 25.3 Crashed after using the Signal Tap Logic AnalyzerDuplicate_hierarchy_depth / duplicate_registerAutomatically added negative node for TDS output doesn't work with Agilex 5