Honored Contributor
Honored ContributorI'm constraining my output RGB interface (33.2 MHz) and that should be kind of easy.
I checked the setup and hold relationships through waveforms in TQ and they should be ok (my latch clock is produced directly from the launch clock through a NOT gate and I can see the inversion). I could find Tsu and Th for my receiving device (they're both 5 ns); for determining my -max and -min output delay value I have to account for delay through the data path and the clock skew. My datas travel on an ATA cable along with the clock, so I have to suppose that the data delay from the FPGA board to the receiver is almost the same of my clock delay. So I could avoid to estimate these probably long delays (which should compensate on both paths) and I should instead estimate my delays as my receiving register was on board, where my GPIO socket is, right? Sorry for the probably stupid questions but I would need a feed to understand if I'm getting correctly the terms of the problem. Anyway, thank you in advance. Regards, Lorenzo
