Defining I/O delay constraints (Timequest)

Most likely.

Source synchronous is surprisingly complex, but I think a lot of that is due to the various situations that can occur. My document is long, but the main bulk deals with four different situations(receiver or transmitter and if the FPGA phase-shifts the clock or not). It then covers a different way of analyzing them that some users like. That's six different cases, whereby you'd really only have to read one of them for a particular interface. They're also very similar too, so once you get the hang of it, hopefully the rest go easily. I believe there is a "quick and dirty" description early on too.

Finally, I realized the altddio blocks are erroring out in Quartus 11.1 when compiling, so if you look at a sample project, you just have to re-generate these blocks. I need to go back in and do this myself and update the example files.