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Altera_Forum
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14 years ago

Defining I/O delay constraints (Timequest)

I'm currently writing timing constraints for my design and, since it's the first time for me with such a big project, I'm having some problems at doing it. I'm using Timequest Timing Analyzer and I'v...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi Rysc, I didn't know about the existence of the document you linked and I thought you left the source-synchronous interfaces argument not discussed yet. Anyway, as I start reading your document, I see that it is not so easy as I supposed.

Maybe I'll clarify my ideas and I'll ask more.

Hi rbugalho, thank you for the explanation: I'm getting it now.

For this moment, I have just another short question: since the whole peripherals on the DE2-115 board are clocked through the FPGA, I suppose that every synchronous interface I'm dealing with (e.g., FLASH, SDRAM, etc.) is a source synchronous one, isn't it right?

Thank you for your help.

Regards,

Lorenzo