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_In the TimeQuest User Guide, p. 19, with reference to the previously discussed commands:
"set_output_delay -clock dac_clk_ext -max 0.0 [get_ports DAC_DATA[5]]
set_output_delay -clock dac_clk_ext -min 0.0 [get_ports DAC_DATA[5]]"
it is said:
"With both -max and -min at 0, we are stating that there are no external delays, and basically have no affect on the analysis."
In my understanding, I would expect these commands to already say that those ports are synchronous to dac_clk_ext clock, so default setup and hold relationships should be applied as the sink registers were into the FPGA. I suppose I'm wrong, but where?
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The set_output_delay constraint describes what happens to the signal once it leaves the chip, using an "ideal" reference. With the constraint above you're telling that the signal DAC_DATA[5]
- after it leaves the FPGA pin, the signal will go through a zero delay
- and then it will be captured at the instant of the rising edge of dac_clk_ext
Ie, you're describing an ideal system where
- there's no delay from the FPGA pin to the DAC pin
- there's no delay from the source* of the dac_clk_ext to the DAC's clock pin
- the DAC input has zero tSU and zero tH
* source, as specified in the create_clock/create_generated_clock constraint.
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