Defining I/O delay constraints (Timequest)

Take a look at the following:

http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest

For a quick overview...

Put a generated clock on the output port that sends the clock off chip, where the source is the PLL output clock. Use that for the -clock option in your set_output_delay. You probably need to add a -invert option to account for your not gate, but double-check your setup and hold margins. I assume your setup relationship should be half a clock period(10ns) and your hold should be negative half a clock period(-10ns). That basically means your data path can vary by +/-10ns and still meet timing. Then add in your external delays to show how much of that margin is chewed up externally.

Also, make sure you run report_timing -detail full_path to the output ports, and make sure your latch clock traces all the way through the FPGA, from the oscillator coming in, through the PLL, through the global, and out your output port. If you see that, then your generated clock is correct(also need to verify the -invert).

As for the read, I'm not sure how you're switching between 50MHz and 33Mhz, but generally you do a set_input_delay where the -clock is the same clock being sent off chip. Your -max value is the total external roundtrip delay max, and the -min is the minimum for this delay.

Again, that's the quick and dirty write-up. Good luck.