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Altera_Forum's avatar
Altera_Forum
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17 years ago

define clock

hello, I want to use a signal for the clock input of a pll. This signal comes from the CDR of the embedded transceiver in the FPGA. The error messages say that I can only drive the pll...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

If you do not send the signal to a general PLL input, but rather JUST to a global clock line in the FPGA, you should be able to do that in the assignment editor.