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Hi,
it makes a difference when you are using Aldec Riviera Pro , it gives an error when you are using Systemverilog statements inside a *.v file.
Regarding your default assignment. I think it's not allowed to assign an input port any value.
see "
http://www.eda.org/sv-bc/hm/att-0595/01-port_connection_rules.pdf" for Systemverilog port connection rules.
Kr,
Florian
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Thank you for your response. I will keep it in mind to always use .sv extension for compatibility with all tools.
I noticed that the pdf file you referenced is dated 06-Mar-2003, so I don't expect it to reflect an enhancement that was added to SystemVerilog in 2009. The enhancement I refer to is the ability to assign a default value to a port left unconnected (rather than have that default be determined merely by the data type, which was the case in 2003). I don't know if I have made a mistake in entering this default value (which seems pretty straightforward in the 2009 documentation), or if Altera is mistaken when they say that Quartus 13.0 supports this section of the SystemVerilog 2009 standard that adds this capability. Perhaps there is something in another section of the 2009 standard that restricts this ability in some way; I don't have access to the standard other than the small section I found online that seemed relevant to my needs.
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