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Altera_Forum
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11 years ago

Default port values in SystemVerilog

I am trying unsuccessfully to define a default value for an input port in a module definition, so that if an instantiation of it does not pass a value to that port, the default value is used without ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Hi,

it makes a difference when you are using Aldec Riviera Pro , it gives an error when you are using Systemverilog statements inside a *.v file.

Regarding your default assignment. I think it's not allowed to assign an input port any value.

see "http://www.eda.org/sv-bc/hm/att-0595/01-port_connection_rules.pdf" for Systemverilog port connection rules.

Kr,

Florian