Alex,
If you already have the encryption key, do the followings:
- Encrypt the design with IEEE 1735. Command line used: encrypt_1735 --quartus --language=verilog counter.v
- File counter.vp will be generated in the file folder.
- Open a new project, add counter.vp in the project. Set it as top-level entity.
- Right click on the counter.vp. Select Properties. Ensure the Type: Verilog HDL File.
- Run Analysis & Synthesis.
Best Regards,
Sheng
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.