Declaring Verilog in VHDL - help!

Hi All,

First post from a novice user...

I'm using Quartus II 13sp1 web edition (Cyclone II so this is the latest I can use) so far I've figured out everything myself and have gotten to the point where I am trying to make use of an OpenCores.org package.

The opencores package is the mod_exp_sim one. Nice thing is it written in VHDL with one Verilog HDL component. As per rd11162011_444 (http://www.altera.com/support/kdb/solutions/rd11162011_444.html) I've created a VHDL based declaration but I keep getting the error:

Error (10476): VHDL error at mod_sim_exp_core.vhd(195): type of identifier "generic_fifo_dc_gray" does not agree with its usage as "entity" type

I've back traced all logic to make sure I've kept the types correct, tried multiple variants (signals, omitting in/out's, etc) and nothing is getting it to compile!

If someone has any ideas how I can make this thing compile. Code attached (didn't cut'n'paste as they are a few hundred lines lone), lines 102->128 are mine.

Any help welcomed!

--

Paul