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Altera_Forum
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15 years ago

Debugging Current State in Simulation (VHDL/Quartus)?

Hey, I've implemented a moore-type finite state machine using process statements and a state variable "y" which holds the current state. TYPE State_type IS (state0,state1,state2...) -- lots of ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Yes, of course I know what the state explicitly SHOULD be according to how I designed it, but I think it would be helpful to be able to explicitly show what state I am in on the vector waveform/simulation results at every point, to troubleshoot why certain outputs don't go high, etc.

Do you understand what I'm asking?