Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Debugging Current State in Simulation (VHDL/Quartus)?

Hey, I've implemented a moore-type finite state machine using process statements and a state variable "y" which holds the current state. TYPE State_type IS (state0,state1,state2...) -- lots of ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Because you declared your own state, you always know what state it is in, because you decalred it.

States dont map to any particular encoding until synthesis. And then you can chose the encoding via the synthesis options.