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Altera_Forum
Honored Contributor
Honored ContributorDe1-SOC SharedOnly Board Package Incompatible with Altera Sample Code
Hello All, I'm a few months into my learning of OpenCL/non-verilog FPGA development and am running across an issue while trying to compile code. Some background specs are as follows: Quartu...
Altera_ForumHonored Contributor
Honored ContributorNo problem. Yea, their initial setup is pretty big where they handle 64x64 blocks of the matrix at a time. On top of that, they're doing floating point mutliplication operations which is expensive. They unroll the section where they do multiply accumulate so that's 64 floating point macc operations implemented in hardware. A simple edit to the host/inc/matrixMult.h file and change the BLOCK_SIZE to maybe 4 or 8 should do the trick.
