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Altera_Forum
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10 years ago

DE0-NANO and Qsys : error when quit Qsys tools

Hi, I begin to use Quartus 15.0 and Qsys. I want create a ADC project. I use Qsys tools. I put CPU : Nios II (Classic) Processor. When I quit Qsys tools, i have this error (I didn't generate): ...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Regarding to the error for reset and exception slave, you will need to connect to an actual memory, either a onchip_memory or DDR. You must not set the reset/exception slave to the jtag_debug_module because that interface is used as for break or debugger operations only.

You can put absolute values but you need to make sure that there is valid memory corresponding to the absolute value.

Usually by design, once you connect a memory to the instruction master, you should be able to select the reset/exception slaves via the drop down box.

Maybe you can refer to the following document: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/tt/tt_nios2_hardware_tutorial.pdf