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Altera_Forum
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14 years ago

DDR3 instantiation, NIOS, Avalon, Qsys

Goal: try to instantiate DDR3 with the DIMM in the Stratix IV E kit (DDR3 with NIOS using Avalon-MM). Goal: try to harness already existing DDR3 Stratix IV E kit work for a new project. The ki...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

in altmemphy (not uniphy) the no. of bits for the local address is calculated for half rate controller as bellow:

For one chip select: width = row bits + bank bits + column bits – 2

For multiple chip selects: width = chip bits + row bits + bank bits + column bits – 2

you should be able to find this information in the controller handbook. the width is different if the controller is working on full rate.

hope this helps