DDR3 instantiation, NIOS, Avalon, Qsys

Thanks for replying.

I will not need NIOS to access 72 bits.

Mostly, I just want to get something to work, but I'm stuck with a 72 bit DIMM.

If it's only 32 bits, that's okay. If it's 64 bits through two 32 bit accesses, that's okay.

Right now I can compile, with Qsys => Quartus,

with a 72 bit DDR3 Qsys UniPHY instantiation.

Looks in the verilog code that the interface is 256 bits (64 * 4 based

on DDR (dual data rate) and then AFI being a half rate interface).

And I can download, and see some signals on signal tap.

The main problem, simply: calibration fails!!!

The interface doesn't work.

Note: I'm using Stratix IV E eval kit board.

This has a working DDR3 design (board test system).

That design uses AltMemPHY, not UniPHY.

I'm trying to match up all my Qsys UniPHY settings to the working

AltMemPHY DDR3 design, but still the calibration fails in HW.