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Altera_Forum
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14 years ago

DDR3 instantiation, NIOS, Avalon, Qsys

Goal: try to instantiate DDR3 with the DIMM in the Stratix IV E kit (DDR3 with NIOS using Avalon-MM). Goal: try to harness already existing DDR3 Stratix IV E kit work for a new project. The ki...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Qsys doesn't support 9-bit symbols (bytes) so enabling 72-bit widths is not going to work. If you plan on sharing this memory with other masters I think a custom bridge would be your best bet. You can expose a subset of the memory span to the CPU and a wide and deep address span to other logic in your design. So the port for the CPU would be exposed to your Qsys system and the wide port would need to be handled outside the system.

Now if you were planning to have Nios II access a 72-bit memory interface then I would stop right there since that doesn't make sense. Nios II has only 32-bit masters so going wider than that just for the CPU is overkill and a waste of logic. Processors typically never access the full width of a DIMM either, those extra 8 bits are reserved for ECC which is handled my the memory controller.