Honored Contributor
Honored ContributorThe Nios II core can only access up to 2GB of data memory and 256MB of instruction memory. So the limitation is the CPU and not the interconnect (which is limited to 4GB per master). If you look at the bitfield encoding of the jump instructions you'll see that it only supports a 26 bit encoding. So 26-bit * 4 bytes/word (instruction master only reads 32-bit words so the lower 2-bits of the address are redundant) equals a 256MB absolute address.
The two easiest ways to address this limitation: 1) Reduce the width of your memory which will in turn reduce it's span. 2) Place the memory behind a windowed bridge. I have seen so many window bridges that one of them must be posted on the forum or alterawiki by now. If you don't find it let me know and I'll see if one is kicking around locally on my computer.
