Honored Contributorhi,
I am using stratixII device and i implemented a ddr2 memory on my board. I want to produce a delay line only for my DQS Read and Write. using a pll for a shift phase can be a good implemantaion but still there is a problem because the pll needs few clocks cycles for locking for every serial strobes he get. Is there is another solution for this implementation. thanks,
Honored ContributorHello axodus,
I have replied to your 2nd thread start for this question. I have deleted your duplicate post for this question dated Aug 10th. There is a DLL in Stratix II devices specifically for delaying and phase shifting DQS during read operation wiht DDR2 memories. A PLL is used to generate the DQS during write based off of the system clock that is always running. Altera DDR2 SDRAM Controller megafunction takes care of this all for you. There is a lot of material in the Stratix II literature section which describes how this works. The ALTDQS megafunction allows you to control the DLL and PLL features if you want to roll your own IP for a controller. I would start here... http://www.altera.com/literature/an/an328.pdf
