The issues I am having are how to set up the tools such that I can measure and meet timing. Basically I can simulate the behavior of my DDR2 controller against the micron model all day long and pass everything. However when I try to compile for the FPGA it will not work.
I have spent weeks trying to figure out cryptic warnings and such from timing tools that 2 or 3 hours with an FAE would have solved.
When I did stuff with Xilinx they would send an FAE out to sit with you for a couple of days to get up to speed on parts. Also they would respond almost immediately with answers to questions. We are going to be doing a lot more designs with FPGAs and even putting things into the "HardCopy." The good thing is that the $3k for the Altera tools was a good price to pay to find out that we should not use Altera.
Again the problem is not the FPGA, it is minor crap. For example I tried to us the ALTDQ and ALTDQS mega functions, however the the ALTDQS does not include simulation code or library thus it was worthless, and of course FAE never responded.
Also I wanted to use the Altera DDR2 controller but they hard coded the chip selects such that they have to be connected to a pin. Where due to physical limit on number of pins we had to use a 74xx138 mux to bring out chip selects for DDR2. Thus we asked the FAE if there was an IP core for the DDR2 we could purchase which would allow us to use more than 8 chips, or if we could purchase Altera's source. Of course here again no response.
Trampas