DDR2 afi_half_clk_reg

Hello,

I'm trying to get a DDR2 with Uniphy system up and running and I keep running into a critical warning regarding the afi_half_clk_reg. Quartus reports that it's missing and the controller won't calibrate. I wasn't planning to use the half rate clock at all and it's indicated as an optional clock in the documentation so I'm not sure why it's causing such a problem

The strange thing is that this only impacts a couple of my designs, some are unaffected. It's the difference between the controller calibrating and not. I can't seem to find the silver bullet here, I've stripped down working and non-working project and can't seem to find the difference that's causing this. Has anyone else run into this before? Any help would be greatly appreciated.

Thanks,

Scott