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the logic which controls the FIFOs read inputs works on the rising edge of CLKOUT, and the FIFO itself works on the falling edge.
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Is there a reason for this? So long as you've setup a TimeQuest .SDC file for the timing analysis and it passes, I guess its ok. However, its not something I've ever needed to do (except perhaps in an I/O element to meet timing).
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Luckily I found the problem myself, and it's quite unrelated to the timing diagram.
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That is why I recommended trying to isolate the problem and posting a testbench. That exercise is usually enough to determine the problem :)
Cheers,
Dave
Honored Contributor
