DCFIFO sample duplication problem

Thank's for Your reply.

The timing diagram is as it should be. As I wrote in the opening post, the logic which controls the FIFOs read inputs works on the rising edge of CLKOUT, and the FIFO itself works on the falling edge.

Luckily I found the problem myself, and it's quite unrelated to the timing diagram. There was a last logic operation with the FIFO_read_req signal right in the instantiation of the FIFO which altered the signal - but this didn't show up in the simulation (because it did not affect the FIFO_write_req register - it did show up in the FIFO itself in the simulation though, which finally helped me to find the error).

Your's sincerely,

Felix Lembcke