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Altera_Forum
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13 years ago

DCFIFO sample duplication problem

Dear fellow forum members, yesterday I encountered a strange problem when simulating a DCFIFO (Altera Megafunction). I attached a picture of the functiuonal simulation, created with Quartus 10...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Something does not look right with your timing diagram.

Look at the signals in the read clock domain. They appear to be half a clock different than the CLKOUT signal, i.e., some logic is using the rising edge, while other logic is using the falling edge.

Try and create a testbench with just the FIFO in it. Reproduce the error and post the testbench code.

Cheers,

Dave