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I filed an enhancement request with Altera asking for something like the "altera message_off" synthesis directive that can suppress a particular message for a particular line of RTL.
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You are my hero Brad :)
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Would there ever be two messages from two different lines of source code that are completely identical (except the line number) without even a node name or entity name in the message text being different?
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Yes, it might happen, because the problem is precisely that some warnings don't mention any node or entity name all. The only "variables" are the source file name and the line number:
Warning (10273): Verilog HDL warning at filename.v(524): extended using "x" or "z"
Warning (10958): SystemVerilog warning at filename.v(829): unique or priority keyword makes case statement complete
Honored Contributor
