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Altera_Forum
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14 years ago

DCFIFO megafunction simulation problem

Hi, I'm attempting to use a DCFIFO megafuction in my design, but, at least during functional simulation (ModelSim-Altera), the last word in the FIFO isn't being read. The rdempty signal asserts...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The usage of fifo is wrong. The entire style of doing such design is wrong. You have to understand what is clock and what there are wrreq and rdreq signals for.