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Altera_Forum
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11 years ago

Cyclone V WYSIWYG primtives are broken :-(

This a rather longish complaint. Maybe someone from Altera reads it and can me give some idea what to do. I am trying to implement my own DDR3 memory controller for a Cyclone V device (in pur...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi Lundril:

I feel your pain, I've came across similar simulation issues with earlier families.

My suggestion is you do the following:

Post a specific issue IE the VHDL simulation model is mission, or incorrect to mysupport

Second contact your distribution partner FAE and get them to push that issue past the front line support personnel. Often the base line support for both Xilinx and Altera is pretty frustrating.. The FAE's vary widely as well, but they at least have contacts into the factory to push the issue up the chain.

If you have an open mysupport case number, they can reference that number and also shadow follow it, so you don't have to describe the issue many times.

The third step is post the issue here, which you did. Depending on the issue, we can be a great help. Unfortunately most of us are not Altera employees. So this particular issue is harder for us to directly fix. :)

Pete