Occasional Contributor
Regular ContributorHello,
The issue seems to be due to 'pll_type' parameter passed to the generic altera_pll component from the IP generated wrapper file cvpll_0002.v, and the assignment to lvds_clk and loaden ports in altera_pll.
For some reason, when dynamic phase shift is enabled, the pll_type = 'Cyclone V', whereas when not enabled, pll_type = 'General'.
The lvds_clk and loaden ports are applicable only for Arria 10 devices. These ports are driven by 0 when pll_type = 'General' or Arria 10 pll ports. For rest of the pll_type values, it is left undriven.
Logically it will not cause any functional issue in your design, so you can safely ignore the warnings.
Regards
Occasional ContributorHello Ash R,
Thank you for your reply. Ok, the PLL does appear to simulate fine, though I do not yet have hardware to prove that. The Quartus warnings arent too bad, however since I am providing my source code to third parties for operation and simulations, how do I explain that the 20 pages of over 300 warnings generated is a problem with Altera/Intel's code and nothing I've done wrong where as my example source for Cyclone IV/Max10 are free of such a huge list of warnings? It covers up/buries the 5-10 pieces of important information I officially try to generate in the transcript during the simulation which verifies my design.
