Forum Discussion

BrianHG's avatar
BrianHG
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Cyclone V PLL issue with dynamic phase shift.

Hello, this is the first test with Cyclone V. I've attached a small Quartus Prime 20.1 project where I configured a PLL with 'Enable access to dynamic phase shift ports' turned on. I'm getting ...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hello,

The issue seems to be due to 'pll_type' parameter passed to the generic altera_pll component from the IP generated wrapper file cvpll_0002.v, and the assignment to lvds_clk and loaden ports in altera_pll.

For some reason, when dynamic phase shift is enabled, the pll_type = 'Cyclone V', whereas when not enabled, pll_type = 'General'.

The lvds_clk and loaden ports are applicable only for Arria 10 devices. These ports are driven by 0 when pll_type = 'General' or Arria 10 pll ports. For rest of the pll_type values, it is left undriven.

Logically it will not cause any functional issue in your design, so you can safely ignore the warnings.


Regards