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BrianM
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Cyclone V: FPGA to SDRAM interface not working

Hello. Part: Cyclone V 5CSXFC5D6F31C7, about 85% utilized. I've written RTL in verilog for a simple MM interface from the FPGA to SDRAM 1 HPS interface. I created a test bench utilizing an MM DRA...
  • BrianM's avatar
    BrianM
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Hi Anil,

    I'm using Quartus 20.1.1 Build 720 on linux.

    That patch only seems to apply to Windows, is there a linux version?

    Thanks,

    Brian