Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Cyclone V: 100% of LABs used in report, but not in Chip Planner

Hi I'm making a design in which I'm seeing some strange differences between the compiler report and what it's seen in the Chip Planner: In the Compiler report, the use of LABs reaches a 10...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I can't really share the design, but I'll start by checking the interconnections usage, if that unused LABs are unreachable that would explain the problem. Thanks!