Cyclone V / MAX 10 ROM

Doing tests I found some unexpected results, same code ( generic Verilog, same project, only changing "device" ) give the following reports. Additionally, the sources show the expected results when simulated on Active-HDL, that means I have a ROM initialized.

Flow Status Successful - Sat Dec 13 10:52:57 2014

Quartus II 64-Bit Version 14.0.2 Build 209 09/17/2014 SJ Web Edition

Family Cyclone V

Device 5CEFA2F23C8

Timing Models Final

Logic utilization (in ALMs) 2,147 / 9,430 ( 23 % )

Total registers 1245

Total pins 99 / 224 ( 44 % )

Total virtual pins 0

total block memory bits 16,384 / 1,802,240 ( < 1 % )

Total DSP Blocks 4 / 25 ( 16 % )

Total HSSI RX PCSs 0

Total HSSI PMA RX Deserializers 0

Total HSSI TX PCSs 0

Total HSSI PMA TX Serializers 0

Total PLLs 1 / 4 ( 25 % )

Total DLLs 0 / 4 ( 0 % )

Flow Status Successful - Sat Dec 13 10:58:57 2014

Quartus II 64-Bit Version 14.0.2 Build 209 09/17/2014 SJ Web Edition

Family MAX 10 FPGA

Device 10M08DAF484C8GES

Timing Models Advance

Total logic elements 4,816 / 8,064 ( 60 % )

Total combinational functions 4,521 / 8,064 ( 56 % )

Dedicated logic registers 1,280 / 8,064 ( 16 % )

Total registers 1280

Total pins 99 / 250 ( 40 % )

Total virtual pins 0

total memory bits 128 / 387,072 ( < 1 % )

Embedded Multiplier 9-bit elements 8 / 48 ( 17 % )

Total PLLs 1 / 2 ( 50 % )

UFM blocks 0 / 1 ( 0 %

The module for ROM nothing special :

module PROM (input clk, input [8:0] adr, output reg [31:0] data);

reg [31:0] mem [511: 0];

initial $readmemh("../prom.mem", mem);

always @(posedge clk) data <= mem[adr];

endmodule

Regards

Walter