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Hi, I am using pll in my design (Cyclone EPC12 speed -8). When I check the fmax in TimeQuest it only shows 117 Mhz. When I generated the PLL the frequency setting is 200 Mhz. My design uses 94% LE, 63% memory bits and 1 PLL. Altera Cyclone handbook mentioned 275 Mhz for -8 speed device (page 4-29, tabel 4-25). What can I do to get the fmax of pll higher than 200?
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fmax applies to registers in fabric and embedded blocks, not PLL.
Essentially you are saying your system clock is 200MHz but your fmax is 117Mhz. You can improve on that by design. Find out the long paths and break them.
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