[Cyclone III] LVDS reciever pll timings

Hi, i have problem, i use Cyclone III to recieve LVDS signal from HD camera, then i mux output with double clock rate, it works but image witch i get is very distorted. There isnt problem with path FPGA->MPU, because when i generate patters in fpga, everything is ok. I think problem are pll timings, i know very little TimeQuest, when i set different pll phase shifts nothing i changing, could you help me? What in my project is wrong?

Regards