Cyclone 5 ay scan in

In order to infer the scan-in port for AY, you need to have associated code that points Quartus in the proper direction for synth + place and route. Options include (Quartus 18.1 standard):

- Quartus IP (i.e. via IP Catalog or Qsys/Platform Designer) - Multiplier Adder Intel FPGA IP

- Inference via RTL templates (see screenshot below)

- Using high-level design tool like DSP Builder

Depends on what are you looking to do with that input port. If there isn't an obvious choice from different tabs/selections in the Quartus IP, it should be able to be done by using the various RTL templates in your source VHDL/Verilog.

The templates are meant to infer a base functionality - can be modified for your specific case, but be aware that changes need to align with the functionality found in the user guide (see link below).

I would recommend first using the Quartus IP GUI - this keeps the scope of the changes to the inferred RTL to valid use-cases.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf

Hopefully this helps!

Jeff