CustomPHY Megafunction generates different ports in component and implementation

Hello,

I am having a problem with using the Custom Transceiver PHY in a simple design. When I create the PHY using the Megafunction Wizard (default options for everything), it creates the implemntation VHDL file with the following entity declaration:

entity customphy_v13 is
    port (
        phy_mgmt_clk         : in  std_logic                      := '0';             --       phy_mgmt_clk.clk
        phy_mgmt_clk_reset   : in  std_logic                      := '0';             -- phy_mgmt_clk_reset.reset
        phy_mgmt_address     : in  std_logic_vector(8 downto 0)   := (others => '0'); --           phy_mgmt.address
        phy_mgmt_read        : in  std_logic                      := '0';             --                   .read
        phy_mgmt_readdata    : out std_logic_vector(31 downto 0);                     --                   .readdata
        phy_mgmt_waitrequest : out std_logic;                                         --                   .waitrequest
        phy_mgmt_write       : in  std_logic                      := '0';             --                   .write
        phy_mgmt_writedata   : in  std_logic_vector(31 downto 0)  := (others => '0'); --                   .writedata
        tx_ready             : out std_logic;                                         --           tx_ready.export
        rx_ready             : out std_logic;                                         --           rx_ready.export
        pll_ref_clk          : in  std_logic_vector(0 downto 0)   := (others => '0'); --        pll_ref_clk.clk
        tx_serial_data       : out std_logic_vector(0 downto 0);                      --     tx_serial_data.export
        pll_locked           : out std_logic_vector(0 downto 0);                      --         pll_locked.export
        rx_serial_data       : in  std_logic_vector(0 downto 0)   := (others => '0'); --     rx_serial_data.export
        tx_clkout            : out std_logic_vector(0 downto 0);                      --          tx_clkout.export
        rx_clkout            : out std_logic_vector(0 downto 0);                      --          rx_clkout.export
        tx_parallel_data     : in  std_logic_vector(7 downto 0)   := (others => '0'); --   tx_parallel_data.export
        rx_parallel_data     : out std_logic_vector(7 downto 0);                      --   rx_parallel_data.export
        reconfig_from_xcvr   : out std_logic_vector(91 downto 0);                     -- reconfig_from_xcvr.reconfig_from_xcvr
        reconfig_to_xcvr     : in  std_logic_vector(139 downto 0) := (others => '0')  --   reconfig_to_xcvr.reconfig_to_xcvr
    );
end entity customphy_v13;

However when I add the block to a block design and create an VHDL file from it, the component delaration in it is as follows

COMPONENT customphy_v13
    PORT(phy_mgmt_clk : IN STD_LOGIC;
         phy_mgmt_clk_reset : IN STD_LOGIC;
         phy_mgmt_read : IN STD_LOGIC;
         phy_mgmt_write : IN STD_LOGIC;
         pll_ref_clk : IN STD_LOGIC;
         rx_serial_data : IN STD_LOGIC;
         phy_mgmt_address : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
         phy_mgmt_writedata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
         reconfig_to_xcvr : IN STD_LOGIC_VECTOR(139 DOWNTO 0);
         tx_parallel_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         phy_mgmt_waitrequest : OUT STD_LOGIC;
         tx_ready : OUT STD_LOGIC;
         rx_ready : OUT STD_LOGIC;
         tx_serial_data : OUT STD_LOGIC;
         pll_locked : OUT STD_LOGIC;
         tx_clkout : OUT STD_LOGIC;
         rx_clkout : OUT STD_LOGIC;
         phy_mgmt_readdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
         reconfig_from_xcvr : OUT STD_LOGIC_VECTOR(91 DOWNTO 0);
         rx_parallel_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    );
END COMPONENT;

Note that some of the ports are of different types. For example the pll_locked port is of type std_logic_vector(0 downto 0) inside the implementation, but of type std_logic inside the component declaration. ModelSim complains about type mismatch when I run my testbench.

Any suggestions why it does this, and how to fix it? I am using Quartus II 13.0 64bit.